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YMF754 ds-1e yamaha corporation december 18, 1998 YMF754 catalog catalog no.:lsi-4mf754a00 june 28, 1999 preliminary overview YMF754 (ds-1e) is a high performance audio controller for the pci bus. ds-1e consists of two separated functional blocks. one is the pci audio block and the other is the legacy audio block. pci audio block provides 64-voice xg wavetable synthesizer with reverb and variation by using the software driver from yamaha. it also supports directsound hardware accelerator, downloadable sound (dls) and directmusic accelerator. legacy audio block supports fm synthesizer, sound blaster pro, mpu401 uart mode and joystick function in order to provide hardware compatibility for numerous pc games on real dos without any software driver. ds-1e supports the connection to ac97 which provides high quality dac, adc and analog mixer, and it can connect two ac97s. in addition, it supports consumer iec958, digital audio interface (spdif in/out), to connect external audio equipment by digital. in addition to support the same functions of ymf744b (ds-1s), ds-1e adds direct recording function for spdif in, and realizes to use spdif in and zoomed video port at the same time. and, ds-1e is featured with the capability of dramatically reducing power consumption at normal operation. features ? pci 2.2 compliant ? pc98 / pc99 specification compliant ? pci bus power management rev. 1.0 compliant (support d0, d2 and d3 state) ? supports clock run ? pci bus master for pci audio true full duplex playback and capture with different sampling rate maximum 64-voice xg capital wavetable synthesizer including gm compatibility directsound hardware acceleration directmusic hardware acceleration downloadable sound (dls) level-1 ? legacy audio compatibility fm synthesizer hardware sound blaster pro compatibility mpu401 uart mode midi interface joystick ? supports pc/pci and distributed dma for legacy dmac (8237) emulation ? supports serialized irq ? supports i 2 s serial input for zoomed video port ? supports consumer iec958 port (spdif in/out) ? supports direct recording function for spdif in ? capability for using spdif in and zoomed video port at the same time. ? supports ac97 interface (ac-link) revision 2.1 ? ac97 digital docking ? supports 4-channel speaker ? hardware volume control ? eeprom interface ? single crystal operation (24.576mhz) ? power supply: 3.3v for i/o (5v tolerant), 2.5v for internal core logic ? 128-pin lqfp YMF754-v : 0.5mm pin pitch YMF754-r : 0.4mm pin pitch the contents of this catalog are target specifications and are subject to change without prior notice. when using this device, please recheck the specifications.
YMF754 june 28, 1999 -2- logos 1. gm system level 1 gm system level 1 is a world standard format about midi synthesizer which provides voice arrangements and midi functions. 2. xg xg is a format about midi synthesizer that is proposed by yamaha, and keeps the upper compatibility of gm system level 1. the good points are the voice arrangements kept extensively, a large number of the voices, modification of the voices, 3 kinds of effects, and so on. 3. sondius-xg products bearing the sondius-xg logo are licensed under patents of stanford university and yamaha corporation as listed on . the s ondius-xg produces acoustic sound outputs by running a virtual simulation of the actual acoustic instrument operation. therefore, it provides much more real-world acoustic sound outputs fundamentally different from the wavetable sound generator that simply processes the recorded acoustic sound sources only. the sondius-xg adds the technology of virtual acoustic sound to the xg format. 4. sensaura sensaura is a technology which provides 3d positional audio and moving effect by hrtf (head related transfer function) with 2 speakers or headphone. this feature makes it possible to enjoy invariable and unchangeable sound feelings in all-positional area covering as wide as 360 degrees. general midi logo is a trademark of association of musical electronics industry (amei), and indicates gm system level 1 compliant. xg logo is a trademark of yamaha corporation. sondius-xg logo is a trademark that stanford university in the united states and yamaha corporation hold jointly. sensaura logo is a trademark of central research laboratories limited.
YMF754 june 28, 1999 -3- pin configuration YMF754-v (0.5mm pin pitch) frame# 1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 cbe2# ad16 ad17 ad18 ad20 ad21 ad22 pvss4 ad23 idsel cbe3# ad24 ad25 pvdd2 pvss3 irdy# trdy# devsel# pvdd1 stop# perr# serr# par cbe1# pvss2 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad19 ad26 ad27 ad28 pvss5 ad29 ad30 ad31 req# gnt# ad7 ad6 ad5 pvdd0 ad4 ad3 ad2 ad1 spdifin gp3 gp4 gp5 gp6 gp7 reserv1 cvdd2 inta# gp1 gp2 test# vss2 vdd1 csdo cbclk csdi0 csync vdd2 cmclk irq5 gpio2 gpio1 gpio0 reserv4 reserv5 reserv6 rst# pvdd3 reserv0 lvss xi24 xo24 loopf spdifout reserv9 reserv10 reserv11 reserv12 zvbclk zvlrck zvsdi pvss1 cbe0# pvss0 ad0 serirq# pcgnt# pcreq# clkrun# cvdd0 romdi romdo/voldw# romsk/volup# romcs reserv8 reserv7 vss0 irq9 irq10 irq11 irq7 cvdd1 lvdd docken# csdi1 reserv3 reserv2 vss1 vdd0 crst# rxd txd gp0 pvss6 pciclk 128 pin lqfp top view
YMF754 june 28, 1999 -4- YMF754-r (0.4mm pin pitch) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 spdifin cbclk csdi0 csync irq5 gpio2 gpio1 gpio0 lvss xi24 xo24 loopf spdifout zvbclk zvlrck zvsdi irq9 irq10 irq11 irq7 cvdd1 lvdd docken# csdi1 reserv3 reserv2 vss1 vdd0 crst# frame# 1 127 126 124 123 122 120 121 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 100 99 98 97 101 102 103 125 128 ad25 pvdd2 ad26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 cbe2# ad16 ad17 ad18 ad20 ad21 ad22 pvss4 ad23 idsel cbe3# ad24 pvss3 irdy# trdy# pvdd1 stop# perr# serr# par cbe1# pvss2 ad15 ad14 ad13 ad12 ad19 devsel# ad27 ad28 pvss5 ad29 ad30 ad31 req# gnt# pciclk rst# pvss6 pvdd3 reserv0 inta# cvdd2 gp7 reserv1 gp6 gp5 gp4 gp3 gp2 gp1 gp0 txd rxd test# vdd2 vss2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 ad8 pvss1 cbe0# ad7 ad6 ad5 pvdd0 ad4 ad3 ad2 ad1 pvss0 ad0 serirq# pcgnt# pcreq# clkrun# cvdd0 romdi romdo/voldw# romsk/volup# romcs vss0 ad11 ad10 ad9 vdd1 cmclk csdo reserv9 reserv10 reserv11 reserv12 reserv8 reserv7 reserv4 reserv5 reserv6 128 pin lqfp top view
YMF754 june 28, 1999 -5- pin description 1. pci bus interface (54-pin) name i/o type size function pciclk i p - pci clock rst# i p - reset ad[31:0] io ptr - address / data c/be[3:0]# io ptr - command / byte enable par io ptr - parity frame# io pstr - frame irdy# io pstr - initiator ready trdy# io pstr - target ready stop# io pstr - stop idsel i p - id select devsel# io pstr - device select req# o p - pci bus master request gnt# i p - pci bus master grant pcreq# o ptr - pc/pci request pcgnt# i ptr - pc/pci grant perr# io pstr - parity error serr# o pod - system error inta# o pod - interrupt signal output for pci bus serirq# io ptr - serialized irq clkrun# io ptr - clock run 2. ac97 interface (8-pin) name i/o type size function crst# o t 6ma reset signal for ac97 cmclk o c - master clock for ac97 (24.576mhz) cbclk i t - ac-link: bit clock for ac97 audio data csdo o t 6ma ac-link: ac97 serial audio output data csync o t 6ma ac-link: ac97 synchronized signal csdi0 i t - ac-link: ac97 serial audio input data (primary) csdi1 i tup - ac-link: ac97 serial audio input data (secondary) docken# i tup - secondary ac97 enable
YMF754 june 28, 1999 -6- 3. external audio interface (5-pin) name i/o type size function spdifout o t 2ma digital audio interface output spdifin i tup - digital audio interface input zvbclk i tup - zoomed video port bit clock zvlrck i tup - zoomed video port l/r clock zvsdi i tup - zoomed video port serial data 4. legacy device interface (15-pin) name i/o type size function irq5 o ttr 6ma interrupt 5 of legacy audio it is directly connected to the interrupt signal of system i/o chip. irq7 o ttr 6ma interrupt 7 of legacy audio irq9 o ttr 6ma interrupt 9 of legacy audio irq10 o ttr 6ma interrupt 10 of legacy audio irq11 o ttr 6ma interrupt 11 of legacy audio. gp[3:0] i a - joystick port gp[7:4] i tup - joystick port rxd i tup - midi data receive txd o t 2ma midi data transfer 5. miscellaneous (11-pin) name i/o type size function romcs o t 2ma chip select for external eeprom romsk / volup# io tup 2ma serial clock for external eeprom or hardware volume (up) romdo / voldw# io tup 2ma serial data output for external eeprom or hardware volume (down) romdi i tup - serial data input for external eeprom xi24 i c - 24.576 mhz crystal xo24 o c - 24.576 mhz crystal loopf i a - capacitor for pll gpio[2:0] io tup 6ma general purpose input / output gpio2 can use for a reset pin of secondary ac97. test# i tup - lsi test pin (do not connect externally.)
YMF754 june 28, 1999 -7- 6. power supply (22-pin) name i/o type size function pvdd[3:0] - - - 3.3v power supply for pci bus interface pvss[6:0] - - - ground for pci bus interface cvdd[2:0] - - - 2.5v power supply for core logic vdd[2:0] - - - 3.3v power supply vss[2:0] - - - ground lvdd - - - 2.5v power supply for pll filter lvss - - - ground for pll filter 7. reserve pin (13-pin) name i/o type size function reserv[12:0] - - - reserve pins (do not connect externally.) type t : ttl a : analog ptr : tri-state pci ttr : tri-state ttl c : cmos pstr : sustained tri-sate pci tup : pull up (max. 300kohm) ttl p : pci pod : open drain pci
YMF754 june 28, 1999 -8- block diagram pci side band pc/pci s-irq audio function config register pci interface legacy audio fm synthesizer sb pro d-dma engine mpu401 joystick pci bus master dma controller pci audio xg synthesizer directsound acc. wave in/out spdif input clock run sampling rate converter (src) spdif output ac-link interface zv port gpio eeprom i/f
YMF754 june 28, 1999 -9- function overview 1. pci interface ds-1e supports the pci bus interface and complies to pci revision 2.2. 1-1. pci bus command ds-1e supports the following pci bus commands. 1-1-1. target device mode c/be[3:0]# command 0000interrupt acknowledge (not su pport) 0001special cycle (not su pport) 0010i/o read 0011i/o write 0100reserved 0101reserved 0110memory read 0111memory write 1000reserved 1001reserved 1010configuration read 1011configuration write 1100memory read mu ltiple (alias to memory read) 1101dual address cycle (not su pport) 1110memory read line (alias to memory read) 1111memory write and invalidate (alias to memory write) ds-1e does not assert devsel# when accessed with commands that are indicated as (not supported) or reserved. 1-1-2. master device mode c/be[3:0]# command 0110memory read 0111memory write when ds-1e becomes a master device, it generates only memory write and read cycle commands.
YMF754 june 28, 1999 -10- 1-2. pci configuration register in addition to the configuration register defined by pci revision 2.2, ds-1e provides proprietary pci configuration registers in order to control legacy audio function, such as fm synthesizer, sound blaster pro, mpu401 and joystick. these additional registers are configured by bios or the configuration software from yamaha corporation. the following shows the overview of the pci configuration register. offset b[31..24] b[23..16] b[15..8] b[7..0] 00-03h device id vendor id 04-07h status command 08-0bh base class code sub class code programming if revision id 0c-0fh reserved header type latency timer reserved 10-13h pci audio memory base address 14-17h legacy audio i/o base address (dummy for sb, fm, mpu, d-dma) 18-1bh legacy audio i/o base address (dummy for joystick) 1c-2bh reserved 2c-2fh subsystem id subsystem vendor id 30-33h reserved 34-37h reserved cap pointer 38-3bh reserved 3c-3fh maximum latency minimum grant interrupt pin interrupt line 40-43h extended legacy audio control legacy audio control 44-47h subsystem id write subsystem vendor id write 48-4bh ds-1e power control 1 ds-1e control 4c-4fh ds-1e power control 2 d-dma slave configuration 50-53h power management capabilities next item pointer capability id 54-57h reserved power management control / status 58-5bh ds-1e secondary ac97 power control acpi mode 5c-5fh reserved 60-63h sound blaster base address fm synthesizer base address 64-67h joystick base address mpu401 base address 68-ffh reserved reserved registers are hardwired to 0. all data written to these registers are discarded. the values read from these registers are all zero. ds-1e can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.
YMF754 june 28, 1999 -11- 00-01h: vendor id read only default: 1073h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vendor id b[15:0] ........vendor id this register contains the yamaha vendor id registered in revision 2.2. this register is hardwired to 1073h . 02-03h: device id read only default: 0012h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 device id b[15:0] ........device id this register contains the device id of ds-1e. this register is hardwired to 0012h . 04-05h: command read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - ser - per - - - bme ms ios b0................ios: i/o space this bit is a dummy one that is capable of writing. this bit indicates for bios or os that ds-1e includes i/o devices. b1................ms: memory space this bit enables ds-1e to response to memory space access. 0: ds-1e ignores memory space access. (default) 1: ds-1e responds to memory space access. b2................bme: bus master enable this bit enables ds-1e to act as a master device on the pci bus. 0: do not set ds-1e to be the master device. (default) 1: set ds-1e to be the master device.
YMF754 june 28, 1999 -12- b6................per: parity error response this bit enables ds-1e responses to parity error. 0: ds-1e ignores all parity errors. (default) 1: ds-1e performs error operation when ds-1e detects a parity error. b8................ser: serr# enable this bit enables ds-1e to drive serr#. 0: do not drive serr#. (default) 1: drives serr# when ds-1e detects an address parity error on normal target cycle or a data parity error on special cycle. 06-07h: status read / write clear default: 0210h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 dpe sse rma rta sta devt dpd - - - cap - - - - b4................cap: capability (read only) this bit indicates that ds-1e supports the capability register. this bit is read only. when 58-59h : acpi mode register, acpi bit is 0, the bit is 1. when acpi bit is 1, the bit is 0. b8................dpd: data parity error detected this bit indicates that ds-1e detects a data parity error during a pci master cycle. b[10:9] ........devt: devsel timing (read only) this bit indicates that the decoding speed of ds-1e is medium. b11..............sta: signaled target abort this bit indicates that ds-1e terminates a transaction with target abort during a target cycle. b12..............rta: received target abort this bit indicates that a transaction is terminated with target abort while ds-1e is in the master memory cycle. b13..............rma: received master abort this bit indicates that a transaction is terminated with master abort while ds-1e is in the master memory cycle. b14..............sse: signaled system error this bit indicates that ds-1e asserts serr#. b15..............dpe: detected parity error this bit indicates that ds-1e detects address parity error or data parity error during a transaction.
YMF754 june 28, 1999 -13- 08h: revision id read only default: 00h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 revision id b[7:0] ..........revision id this register contains the revision number of ds-1e. this register is hardwired to 00h . 09h: programming interface read only default: 00h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 programming interface b[7:0] ..........programming interface this register indicates the programming interface of ds-1e. this register is hardwired to 00h . 0ah: sub-class code read only default: 01h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 sub-class code b[7:0] ..........sub-class code this register indicates the sub-class of ds-1e. this register is hardwired to 01h . ds-1e belongs to the audio sub-class. 0bh: base class code read only default: 04h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 base class code b[7:0] ..........base class code this register indicates the base class of ds-1e. this register is hardwired to 04h . ds-1e belongs to the multimedia base class.
YMF754 june 28, 1999 -14- 0dh: latency timer read / write default: 00h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 latency timer b[7:0] ..........latency timer when ds-1e becomes a bus master device, this register indicates the initial value of the master latency timer. 0eh: header type read only default: 00h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 header type b[7:0] ..........header type this register indicates the device type of ds-1e. this is hardwired to 00h . 10-13h: pci audio memory base address read / write default: 00000000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 mba - - - - - - - - - - - - - - - b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 mba (higher) b[31:15] ......mba: memory base address this register indicates the physical memory base address of the pci audio registers in ds-1e. the base address can be located anywhere in the 32-bit address space. data in the ds-1e register is not prefetchable. size of the register to be mapped into the memory space is 32,768 bytes.
YMF754 june 28, 1999 -15- 14-17h: legacy audio i/o base address (dummy for sb, fm, mpu, d-dma) read / write default: 00000001h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 iobase0 - - - - - i/o b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 - - - - - - - - - - - - - - - - b0................io (read only) this bit indicates that the base address is assigned to i/o. this bit is hardwired to 1. b[15:6] ........iobase0 this register is used so that the os may secure i/o resources for sound blaster pro, fm synthesizer, mpu401 and d-dma controller. because this register is a dummy one, each for the i/o addresses of the above blocks is assigned with the i/o addresses set to 4c-4dh and 60-65h respectively by the software driver. 18-1bh: legacy audio i/o base address (dummy for joystick) read / write default: 00000001h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 iobase1 - i/o b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 - - - - - - - - - - - - - - - - b0................io (read only) this bit indicates that the base address is assigned to i/o. this bit is hardwired to 1. b[15:2] ........iobase1 this register is used so that the os may secure i/o resource for the joystick port. because this register is a dummy one, the joystick i/o address is assigned with the i/o address set to 66-67h by the software driver.
YMF754 june 28, 1999 -16- 2c-2dh: subsystem vendor id read only default: 1073h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 subsystem vendor id b[15:0] ........subsystem vendor id this register contains the subsystem vendor id. in general, this id is used to distinguish adapters or systems made by different ihvs using the same chip by the same vendor. this register is read only. to write the ihvs vendor id, use 44-45h (subsystem vendor id write register). ihvs must change this id to their vendor id in the bios post routine. in case of the system such as sound card which bios can not control, this id can be changed by connecting eeprom externally. then, subsystem vendor id write register is invalid. in case eeprom is not externally, the default value is the yamaha's vendor id, 1073h . 2e-2fh: subsystem id read only default: 0012h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 subsystem id b[15:0] ........subsystem id this register contains the subsystem id. in general, this id is used to distinguish adapters or systems made by different ihvs using the same chip by the same vendor. this register is read only. to write the ihv's device id, use 46-47h (subsystem id write register). ihvs must change this id to their id in the bios post routine. in case of the system such as sound card which bios can not control, this id can be changed by connecting eeprom externally. then, subsystem id write register is invalid. in case eeprom is not externally, the default value is the yamaha's device id, 0012h . 34h: capability register pointer read only default: 50h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 capability register pointer b[7:0] ..........capability register pointer this register indicates the offset address of the capabilities register in the pci configuration register when 58-59h: acpi mode register, acpi bit is 0. ds-1e provides pci bus power management registers as the capabilities. the power management registers are mapped to 50h - 55h in the pci configuration register, and this register indicates 50h. when acpi bit is 1, this register indicates 00h.
YMF754 june 28, 1999 -17- 3ch: interrupt line read / write default: 00h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 interrupt line b[7:0] ..........interrupt line this register indicates the interrupt channel that inta# is assigned to. 3dh: interrupt pin read only default: 01h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 interrupt pin b[7:0] ..........interrupt pin ds-1e supports inta# only. this register is hardwired to 01h. 3eh: minimum grant read only default: 05h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 minimum grant b[7:0] ..........minimum grant this register indicates the length of the burst period required by ds-1e. this register is hardwired to 05h . 3fh: maximum latency read only default: 19h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 maximum latency b[7:0] ..........maximum latency this register indicates how often ds-1e generates the bus master request. this register is hardwired to 19h .
YMF754 june 28, 1999 -18- 40-41h: legacy audio control read / write default: 907fh access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lad sien mpuirq sbirq sdma i/o mien men jpen fmen sben b0................sben: sound blaster enable this bit enables the mapping of the sound blaster pro block in the i/o space specified by 62-63h: sound blaster base address register, when lad is set to 0. 0: disable the mapping of the sb block to the i/o space 1: enable the mapping of the sb block to the i/o space (default) b1................fmen: fm synthesizer enable this bit enables the mapping of the fm synthesizer block in the i/o space specified by 60-61h: fm synthesizer base address register when lad is set to 0. fm synthesizer registers can be accessed via sb i/o space, while the sb block is enabled, even if fmen is set to 0. 0: disable the mapping of the fm synthesizer block to the fmio space 1: enable the mapping of the fm synthesizer block to the fmio space (default) after setting fmen to 1, about 100 msec is necessary before accessing these i/o space. b2................jpen: joystick port enable this bit enables the mapping of the joystick block in the i/o space specified by 66-67h: joystick base address register, when lad is set to 0. 0: disable the mapping of the joystick block 1: enable the mapping of the joystick block (default) b3................men: mpu401 enable this bit enables the mapping of the mpu401 block in the i/o space specified by 64-65h: mpu401 base address register, when lad is set to 0. 0: disable the mapping of the mpu401 block 1: enable the mapping of the mpu401 block (default) b4................mien: mpu401 irq enable this bit enables the interrupt service of mpu401, when lad is set to 0 and men is set to 1. mpu401 generates an interrupt signal when it receives any kind of midi data from the rxd pin. 0: the mpu401 block can not use the interrupt service. 1: the mpu401 block can use interrupt signals determined by the mpuirq bits. (default) b5................i/o: i/o address aliasing control this bit selects the number of bits to decode for the i/o address of each block. 0: 16-bit address decode 1: 10-bit address decode (default)
YMF754 june 28, 1999 -19- b[7:6] ..........sdma: sound blaster dma-8 channel select these bits select the dma channel for the sound blaster pro block. 0: dma ch0 1: dma ch1 (default) 2: reserved 3: dma ch3 b[10:8] ........sbirq: sound blaster irq channel select these bits select the interrupt channel for the sound blaster pro block. 0: irq5 (default) 1: irq7 2: irq9 3: irq10 4: irq11 5 - 7: reserved. b[13:11] ......mpuirq: mpu401 irq channel select when mien is set to 1, these bits select the interrupt channel for the mpu401 block. 0: irq5 1: irq7 2: irq9 (default) 3: irq10 4: irq11 5 - 7: reserved same interrupt channels can be assigned to sbirq and mpuirq. b14..............sien: serialized irq enable ds-1e supports 3 types of interrupt protocols: pci interrupt (inta#), legacy interrupt (irqs) and serialized irq. the interrupt protocol is selected with imod and sien as follows. the interrupt channels for irqs and serialized irq are determined by sbirq and mpuirq,. only one protocol can be used at once. sien imod interrupt protocol 0 0 legacy interrupt (irqs) (default) 0 1 pci interrupt (inta#) 1 0 serialized irq 1 1 reserved
YMF754 june 28, 1999 -20- b15..............lad: legacy audio disable this bit disables the legacy audio block. 0: enables the legacy audio block 1: disables the legacy audio block (default) when this bit is set to 1, ds-1e does not respond to the i/o target transaction for legacy i/o address on the pci bus. 42-43h: extended legacy audio control read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 imod sbver smod - - maim - - - - - - - - b8................maim: mpu401 acknowledge interrupt mask this bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing mpu401 mode form default to uart, is returned. 0: interrupt is asserted when the acknowledge is returned. (default) 1: interrupt is masked when the acknowledge is returned. b[12:11] ......smod: sb dma mode these bits determine the protocol to achieve the dmac(8237) function on the pci bus. 0: pc/pci (default) 1: reserved 2: distributed dma (d-dma) 3 reserved b[14:13] ......sbver: sb version select these bits set the version of the sb pro dsp. the value set in these bits is returned by sending the e1h dsp command. 0: ver 3.01 (default) 1: ver 2.01 2: ver 1.05 3: reserved b15..............imod: legacy irq mode the legacy interrupt protocol is selected with imod and sien. refer to the explanation of sien bit.
YMF754 june 28, 1999 -21- 44-45h: subsystem vendor id write read / write default: 1073h access bus width: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 subsystem vendor id write b[15:0] ........subsystem vendor id write this register sets the subsystem vendor id that is read from 2c-2dh (subsystem vendor id register). the default value is the yamaha vendor id, 1073h . ihvs must change this id to their vendor id in the bios post routine. in case eeprom connects externally, this register is invalid, and do not reflect to subsystem vendor id. 46-47h: subsystem id write read / write default: 0012h access bus width: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 subsystem id write b[15:0] ........subsystem id write this register sets the subsystem id that is read from 2e-2fh (subsystem id register). the default value is the ds-1e device id, 0012h . ihvs must change this id to their id in the bios post routine. in case eeprom connects externally, this register is invalid, and do not reflect to subsystem id. 48-49h: ds-1e control read / write default: 0001h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - - - - - acls wrst - crst b0................crst: ac97 software reset signal control this bit controls the crst# signal. 0: inactive (crst#=high) 1: active (crst#=low) (default)
YMF754 june 28, 1999 -22- b2................wrst: ac97 warm reset this bit places the ac97 in warm reset condition when the bit_clk signal on the ac97 remains in inactive state. if this bit is set to 1, it will automatically return to 0 after 1.3s time duration. this bit is valid only while the acls bit is set to 0. except in this case, even if this bit is attempted to be set to 1, no warm reset will be generated (write operation of 1 remains disabled). 0: normal (default) 1: ac97 warm reset b3................acls: ac-link status (read only) this bit indicates whether or not the ac-link is active. this bit is 1 when the ac-link remains in active state (the bit_clk signal is active). 0: ac97 inactive (default) 1: ac97 active 4a-4bh: ds-1e power control 1 read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 - jsr - - - dpll - dmc b0................dmc: disable master clock oscillation setting this bit to 1 disables the oscillation of the master clock (24.576 mhz). 0: normal (default) 1: disable b2................dpll: disable pll clock oscillation setting this bit to 1 disables the oscillation of pll. 0: normal (default) 1: disable b6................jsr: joystick reset this bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port. the initial value is set to 0 immediately after power on reset or hardware reset. 0: normal (default) 1: resets the flip-flop circuit following the analog comparator stage on the joystick port b8................pr0: ac97 power down control 0 this bit controls the power state of the adc and input mux in the primary ac97. 0: normal (default) 1: power down
YMF754 june 28, 1999 -23- b9................pr1: ac97 power down control 1 this bit controls the power state of the dac in the primary ac97. 0: normal (default) 1: power down b10..............pr2: ac97 power down control 2 this bit controls the power state of the analog mixer (vref still on) in the primary ac97. this power state retains the reference voltage of the ac97. 0: normal (default) 1: power down b11..............pr3: ac97 power down control 3 this bit controls the power state of the analog mixer (vref off) in the primary ac97. this power state removes reference voltage of the ac97. 0: normal (default) 1: power down b12..............pr4: ac97 power down control 4 this bit controls the power state of the ac-link in the primary ac97. 0: normal (default) 1: power down b13..............pr5: ac97 power down control 5 setting this bit to 1 disables the internal clock of the primary ac97. in case the ac97 is used with ds-1e, the master clock is supplied from ds-1e. therefore, when the clock is stopped completely, set pr5 bits to 1 firstly, then the cmcd bit should be set to 1 after duration of 1ms or longer. 0: normal (default) 1: disable b14..............pr6: ac97 power down control 6 this bit controls pr6 bit status of the power control register in the primary ac97. b15..............pr7: ac97 power down control 7 this bit controls pr7 bit status of the power control register in the primary ac97. respective data set to b[15:8] are correspondingly set into the power down ctrl/stat register in the primary ac97 via the ac-link. these are not set into the power down ctrl/stat register in the secondary ac97.
YMF754 june 28, 1999 -24- 4c-4dh: d-dma slave configuration read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 base address ea ts ce b0................ce: channel enable this bit enables the distributed dma function. 0: disable distributed dma (default) 1: enable distributed dma b[2:1] ..........ts: transfer size (read only) these bits indicate the size of the dma transfer. since ds-1e supports only 8-bit dma transfer, the bits are hardwired to 00b. b3................ea: extended address (read only) ds-1e does not support extended address mode. this bit is hardwired to 0b. b[15:4] ........base address : d-dma slave base address these bits indicate the d-dma slave base address. 4e-4fh: ds-1e power control 2 read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - pshwv psio psacl psdir psdit pszv pssrc pspca psjoy psmpu pssb psfm cmcd b0................cmcd: codec master clock disable setting this bit to 1 disables the oscillation of the cmclk. to stop a clock, when the cmclk is supplied to the ac97, it is required that b13:pr5 bit of 4a-4bh register is set to 1. (if the secondary ac97 is used, it is also necessary that b5:spr5 bit of 5a-5bh register is set to 1.) 0: normal (default) 1: disable b1................psfm: power save fm synthesizer setting this bit to 1 stops a clock supplied to the fm synthesizer block. 0: normal (default) 1: disable b2................pssb: power save sound blaster setting this bit to 1 stops a clock supplied to the sound blaster block. 0: normal (default) 1: disable
YMF754 june 28, 1999 -25- b3................psmpu: power save mpu401 setting this bit to 1 stops a clock supplied to the mpu401 block. 0: normal (default) 1: disable b4................psjoy: power save joystick setting this bit to 1 disables the comparator of the joystick block. 0: normal (default) 1: disable b5................pspca: power save pci audio setting this bit to 1 stops a clock supplied to the pci audio block. 0: normal (default) 1: disable b6................pssrc: power save src setting this bit to 1 stops a clock supplied to the src block. 0: normal (default) 1: disable b7................pszv: power save zoomed video port setting this bit to 1 stops a clock supplied to the zoomed video port block. 0: normal (default) 1: disable b8................psdit: power save digital audio interface transmitter setting this bit to 1 stops a clock supplied to the dit (spdif out) block. 0: normal (default) 1: disable b9................psdir: power save digital audio interface receiver setting this bit to 1 stops a clock supplied to the dir (spdif in) block. 0: normal (default) 1: disable b10..............psacl: power save ac-link setting this bit to 1 stops a clock supplied to the ac-link block. 0: normal (default) 1: disable
YMF754 june 28, 1999 -26- b11..............psio: power save i/o pad setting this bit to 1 cuts the pull up resistor of the input pins except for the pci interface and ac-link. the input signals keep the level before psio bit is set from 0 to 1. in case the input level is only low, the pull up resistor is cut. 0: normal (default) 1: cuts the pull up resistor b12..............pshwv: power save hardware volume setting this bit to 1 stops a clock supplied to the hardware volume block. 0: normal (default) 1: disable pci clock (33mhz) pci i/f pc/pci d-dma s-irq eeprom i/f i/o pad psio external input master clock (24.576mhz) pll dmc dpll fm synthesizer sb pro ac-link zvport h/w vol. pci audio src spdif out spdif in ac97 master clock mpu401 joystick cmcd psfm pssb psmpu psjoy pspca pssrc pszv psdit psdir psacl pshwv power management block
YMF754 june 28, 1999 -27- 50h: capability id read only default: 01h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 capability id b[7:0] ..........capability id: capability identifier this register indicates that the new capability register is for power management control. this register is hardwired to 01h . 51h: next item pointer read only default: 00h access bus width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 next item pointer b[7:0] ..........next item pointer ds-1e does not provide other new capability besides power management. this register is hardwired to 00h . 52-53h: power management capabilities read only default: 0401h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - d2s - - - - - - - version b[2:0] ..........version these bits contain the revision number of the power management interface specification. they are hardwired to 001b . b10..............d2s: d2 support this bit indicates that ds-1e support d2 of the power state. it is hardwired to 1.
YMF754 june 28, 1999 -28- 54-55h: power management control / status read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - - - - - - - ps b[1:0] ..........ps: power state these bits determine the power state of ds-1e. ds-1e supports the following power states: 0: d0 1: d1 (not supported) 2: d2 3: d3 hot when the power state is changed from d3 hot to d0, ds-1e resets the pci configuration register 00-3fh. ds-1e transits to d0 uninitialized state. though the power state of this register is changed, the power consumption of ds-1e is not changed. to support low power, windows driver controls ds-1e power control 1 / ds-1e power control 2 / ds-1e control / ds-1e secondary ac97 power control registers. ds-1e can support the power state of d0, d1, d2 and d3 with acpi. in this case, set acpi bit (58-59h: acpi mode register) to 1 to disable capabilities of pci bus power management. 58-59h: acpi mode read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - - - - - - - - acpi b0................acpi: acpi mode select this bit select either pci bus power management or acpi mode for power management of ds-1e. 0: pci bus power management is used. cap bit (06-07h: status register) and capabilities pointer (34h) are enabled. (default) 1: acpi mode is used. cap bit and capabilities pointer are hardwired 0, and disabled. 5a-5bh: ds-1e secondary ac97 power control read / write default: 0000h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - spr7 spr6 spr5 spr4 spr3 spr2 spr1 spr0 b0................spr0: secondary ac97 power down control 0 this bit controls the power state of the adc and input mux in the secondary ac97. 0: normal (default) 1: power down
YMF754 june 28, 1999 -29- b1................spr1: secondary ac97 power down control 1 this bit controls the power state of the dac in the secondary ac97. 0: normal (default) 1: power down b2................spr2: secondary ac97 power down control 2 this bit controls the power state of the analog mixer (vref still on) in the secondary ac97. this power state retains the reference voltage of the ac97. 0: normal (default) 1: power down b3................spr3: secondary ac97 power down control 3 this bit controls the power state of the analog mixer (vref off) in the secondary ac97. this power state removes reference voltage of the ac97. 0: normal (default) 1: power down b4................spr4: secondary ac97 power down control 4 this bit controls the power state of the ac-link in the secondary ac97. 0: normal (default) 1: power down b5................spr5: secondary ac97 power down control 5 setting this bit to 1 disables the internal clock of the secondary ac97. in case the ac97 is used with ds-1e, the master clock is supplied from ds-1e. therefore, when the clock is stopped completely, set spr5 bits to 1 firstly, then the cmcd bit should be set to 1 after duration of 1ms or longer. 0: normal (default) 1: disable b6................spr6: secondary ac97 power down control 6 this bit controls pr6 bit status of the power control register in the secondary ac97. b7................spr7: secondary ac97 power down control 7 this bit controls pr7 bit status of the power control register in the secondary ac97. respective data set to b[7:0] are correspondingly set into the power down ctrl/stat register in the secondary ac97 via the ac-link. these are not set into the power down ctrl/stat register in the primary ac97.
YMF754 june 28, 1999 -30- 60-61h: fm synthesizer base address read / write default: 0388h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 fm synthesizer base address - - b[15:2] ........fm synthesizer base address this register sets the base address of the fm synthesizer. if b5:i/o bit of 40h register is set to 1, b[9:2] bits are decoded by ignoring b[15:10] bits. 62-63h: sound blaster base address read / write default: 0220h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sound blaster base address - - - - b[15:4] ........sound blaster base address this register sets the base address of the sound blaster. if b5:i/o bit of 40h register is set to 1, b[9:4] bits are decoded by ignoring b[15:10] bits. 64-65h: mpu401 base address read / write default: 0330h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 mpu401 base address - b[15:1] ........mpu401 base address this register sets the base address of the mpu401. if b5:i/o bit of 40h register is set to 1, b[9:1] bits are decoded by ignoring b[15:10] bits. 66-67h: joystick base address read / write default: 0201h access bus width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 joystick base address b[15:0] ........joystick base address this register sets the base address of the joystick. if b5:i/o bit of 40h register is set to 1, b[9:0] bits are decoded by ignoring b[15:10] bits.
YMF754 june 28, 1999 -31- 2. isa compatible device ds-1e contains the following functions to maintain the compatibility with the past isa sound devices. these devices are considered legacy devices and the functions are referred to as legacy audio. legacy audio is independent from pci audio and can be used simultaneously. the configuration is set in the legacy audio control register in the pci configuration register space. basically, these registers are configured by the bios. also, logical device ids are assigned to the devices to support plug and play. yamaha defines the following logical ids. to control the device with the bios, the logical device ids must be defined in the pnp bios extended rom space. the logical ids are determined by how it is configured. ids and configuration are as follows. functions used (block) logical device id fm (*) mpu401 sb pro (*) joystick ymh0100 o o o ymh0101 o ymh0102 o ymh0103 o ymh010a o o * the blocks pertain to the following. fm: points to the fm synthesizer mapped to adlibbase (0x0388). sb pro: points to the voice playback section only. these devices are independent from each other, and can be enabled/disabled individually. however, both adlib and sound blaster must be disabled to disable the internal fm synthesizer. disabling just adlib only masks the access. the driver by yamaha supports logical device id, ymh0100, ymh0102, ymh0103 and ymh010a. for ymh0101, use the driver provided by microsoft.
YMF754 june 28, 1999 -32- ds-1e supports pc/pci and d-dma protocols to emulate the dma of sb pro on the pci. in addition, ds- 1e supports the old type of interrupts used by isa and the serialized irq protocol. the combination of pc/pci and serialized irq is recommended for ds-1e. the system block diagram when using intel chip set is shown below. irq11 irq10 irq9 irq7 pcreq# irq5 pcgnt# south bridge (piix4e) pci control address/data north brigde (430tx/440bx) serirq# select either protocols ds-1e the pci-to-isa bridge needs to support pc/pci. irq is directly connected to the irq input pins on the pci-to-isa bridge.
YMF754 june 28, 1999 -33- 2-1. fm synthesizer block fm synthesizer block is register compatible with ymf289b. however, power management register has been deleted because it is now controlled by the pci configuration register. the following shows the fmbase i/o map of fm synthesizer. fmbase (r) status register port fmbase (w) address port for register array 0 fmbase+1 (r/w) data port fmbase+2 (w) address port for register array 1 fmbase+3 (r/w) data port the following shows the fm synthesizer block registers. 2-1-1. status register fm synthesizer status register (ro): addressd7d6d5d4d3d2d1d0 xxh irq ft1 ft2 - - busy - busy
YMF754 june 28, 1999 -34- 2-1-2. fm synthesizer data register fm synthesizer data register array 0 (r/w): addressd7d6d5d4d3d2d1d0 00-01h lsi test 02h timer 1 03h timer 2 04h rst mt1 mt2 - - - st2 st1 08h-nts------ 20-35h (*1) am vib egt ksr mult 40-55h (*2) ksl tl 60-75h (*3) ar dr 80-95h (*4) sl rr a0-a8h f-num (l) b0-b8h - - kon block f-num (h) bdh dam dvb rhy bd sd tom tc hh c0-c8h (*6) (*6) chr chl fb cnt e0-f5h (*5) ----- ws fm synthesizer data register array 1 (r/w) addressd7d6d5d4d3d2d1d0 00-01h lsi test 04h - - connection sel 05h - - - - - (*6) (*6) new 20-35h (*1) am vib egt ksr mult 40-55h (*2) ksl tl 60-75h (*3) ar dr 80-95h (*4) sl rr a0-a8h f-num (l) b0-b8h - - kon block f-num (h) c0-c8h (*6) (*6) chr chl fb cnt e0-f5h (*5) ----- ws *1 : 26h, 27h, 2eh and 2fh do not exist. *2 : 46h, 47h, 4eh and 4fh do not exist. *3 : 66h, 67h, 6eh and 6fh do not exist. *4 : 86h, 87h, 8eh and 8fh do not exist. *5 : e6h, e7h, eeh and efh do not exist. *6 : the bits exist, but do not function.
YMF754 june 28, 1999 -35- 2-2. sound blaster pro block sound blaster pro block emulates the dsp commands of sound blaster and sound blaster pro. only playback functions are supported (record functions are not supported). however, to maintain compatibility for games, it is designed so that every dsp command receives a correct response. the dma transfer of this block uses pc/pci or d-dma protocol. the following shows the sbbase i/o map of sb pro. sbbase (r) fm synthesizer status port sbbase (w) fm synthesizer address port for register array 0 sbbase+1h (r/w) fm synthesizer data register sbbase+2h (w) fm synthesizer address port for register array 1 sbbase+3h (r/w) fm synthesizer data port sbbase+4h (r/w) sb mixer address port sbbase+5h (r/w) sb mixer data port sbbase+6h (w) sb dsp reset port sbbase+8h (r) fm synthesizer status port sbbase+8h (w) fm synthesizer address port for register array 0 sbbase+9h (r/w) fm synthesizer data port sbbase+ah (r) dsp read data port sbbase+ch (r) dsp write-buffer status port sbbase+ch (w) dsp write command/data port sbbase+eh (r) dsp read-buffer status port
YMF754 june 28, 1999 -36- 2-2-1. dsp command the following shows the list of dsp commands that are supported by the sb pro engine. both sb and sb pro commands are supported. cmd support function 10h o 8bit direct mode single byte digitized sound output 14h o 8bit single-cycle dma mode digitized sound output 16h 8bit to 2bit adpcm single-cycle dma mode digitized sound output 17h 8bit to 2bit adpcm single-cycle dma mode digitized sound output with ref. byte 1ch o 8bit auto-init dma mode digitized sound output 1fh 8bit to 2bit adpcm auto-init dma mode digitized sound output with ref. byte 20h(*1) o 8bit direct mode single byte digitized sound input 24h(*1) o 8bit single-cycle dma mode digitized sound input 2ch(*1) o 8bit auto-init dma mode digitized sound input 30h o polling mode midi input 31h o interrupt mode midi input 34h o uart polling mode midi i/o 35h o uart interrupt mode midi i/o 36h(*2) o uart polling mode midi i/o with time stamping 37h(*2) o uart interrupt mode midi i/o with time stamping 38h o midi output 40h o set digitized sound transfer time constant 48h o set dsp block transfer size 74h o 8bit to 4bit adpcm single-cycle dma mode digitized sound output 75h o 8bit to 4bit adpcm single-cycle dma mode digitized sound output with ref. byte 76h 8bit to 3bit adpcm single-cycle dma mode digitized sound output 77h 8bit to 3bit adpcm single-cycle dma mode digitized sound output with ref. byte 7dh o 8bit to 4bit adpcm auto-init dma mode digitized sound output with ref. byte 7fh 8bit to 3bit adpcm auto-init dma mode digitized sound output with ref. byte 80h o pause dac for a duration 90h o 8bit high-speed auto-init dma mode digitized sound output 91h o 8bit high-speed single-cycle dma mode digitized sound output 98h(*1) o 8bit high-speed auto-init dma mode digitized sound input 99h(*1) o 8bit high-speed single-cycle dma mode digitized sound input a0h(*1) o set input mode to mono a8h(*1) o set input mode to stereo d0h o pause 8bit dma mode digitized sound i/o d1h(*3) o turn on speaker d3h(*3) o turn off speaker d4h o continue 8bit dma mode digitized sound i/o d8h o get speaker status dah o exit 8bit auto-init dma mode digitized sound i/o e1h o get dsp version number note: (*1) the sb block responds correctly to the commands for recording and also executes the dma transfer. 80h is always transferred. (*2) only output is supported for this command. (*3) this command only changes speaker status (d8h). undocumented commands other than the ones listed above are also supported.
YMF754 june 28, 1999 -37- 2-2-2. sound blaster pro mixer the following shows the register map of the mixer section of sound blaster pro. addressb7b6b5b4b3b2b1b0 remark 00h reset 04h voice volume l "1" voice volume r "1" 0ah - - - "1" - mic volume* 0ch - - ifilter* "1" input source* "1" 0eh - - ofilter* "1" - - st. sw "1" 22h master volume l "1" master volume r "1" 26h midi volume l "1" midi volume r "1" 28h cd volume l* "1" cd volume r* "1" 2eh line volume l* "1" line volume r* "1" sb pro mixer f0h sbpda - - - ss sm se sbpdr f1h scan data f2h current fm synthesizer index f3h - - - - - - - cfa f4h ffemp ffful - - - - - mpus suspend / resume f8h - - - - - - - sbi irq status the registers marked with * exist, but do not function. ds-1e does not have the circuit that corresponds to the sb mixer. therefore, the volume settings on the sb mixer are converted to the dsp coefficients of ds-1e or to ac97 register values. the conversion for each case is described below. (1) sb mixer ? dsp the volume of master, midi and voice, are applied to this case. when the sb register is set, a 14-bit coefficient value is determined from the following conversion table and used as the dsp coefficient. the attenuation value of master volume, midi, and voice are summed together to obtain the coefficient. these volumes cannot be controlled from pci audio block.
YMF754 june 28, 1999 -38- (1) volume for midi midi vol. (26h) 01234567 mute mute mute mute mute mute mute mute 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mute -52db -42db -36db -32db -30db -28db -26db 1 0000h 0029h 0082h 0103h 019bh 0206h 028ch 0335h mute -42db -32db -26db -22db -20db -18db -16db 2 0000h 0082h 019bh 0335h 0515h 0666h 080eh 0a24h mute -36db -26db -20db -16db -14db -12db -10db 3 0000h 0103h 0335h 0666h 0a24h 0cc5h 1013h 143dh mute -32db -22db -16db -12db -10db -8db -6db 4 0000h 019bh 0515h 0a24h 1013h 143dh 197ah 2013h mute -30db -20db -14db -10db -8db -6db -4db 5 0000h 0206h 0666h 0cc5h 143dh 197ah 2013h 2861h mute -28db -18db -12db -8db -6db -4db -2db 6 0000h 028ch 080eh 1013h 197ah 2013h 2861h 32d6h mute -26db -16db -10db -6db -4db -2db 0db master vol. (22h) 7 0000h 0335h 0a24h 143dh 2013h 2861h 32d6h 3fffh the default is master = 4, midi = 4 (-12db). (2) volume for voice voice vol. (04h) 01234567 mute mute mute mute mute mute mute mute 0 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mute -56db -46db -40db -36db -34db -32db -30db 1 0000h 0019h 0052h 00a3h 0103h 0146h 019bh 0206h mute -46db -36db -30db -26db -24db -22db -20db 2 0000h 0052h 0103h 0206h 0335h 0409h 0515h 0666eh mute -40db -30db -24db -20db -18db -16db -14db 3 0000h 00a3h 0206h 0409h 0666h 080eh 0a24h 0cc5h mute -36db -26db -20db -16db -14db -12db -10db 4 0000h 0103h 0335h 0666h 0a24h 0cc5h 1013h 143dh mute -34db -24db -18db -14db -12db -10db -8db 5 0000h 0146h 0409h 080eh 0cc5h 1013h 143dh 197ah mute -32db -22db -16db -12db -10db -8db -6db 6 0000h 019bh 0515h 0a24h 1013h 143dh 197ah 2013h mute -30db -20db -14db -10db -8db -6db -4db master vol. (22h) 7 0000h 0206h 0666h 0cc5h 143dh 187ah 2013h 2861h the default is master = 4, voice = 4 (-16db). (2) sb mixer ? ac97 the volume of cd, line and mic are applied to this case. ac97 volume are not updated automatically when these values are changed. thus, the sb mixer values need to be written to the ac97 register with the software.
YMF754 june 28, 1999 -39- 2-2-3. sb suspend / resume the sb block can read the internal state as to support suspend and resume functions. the internal state is made up of 268 flip flops. to read the state, these states are shifted in order and read 8 bits at a time from the scan data register. these registers are mapped to the sb mixer space (see sb mixer register map). the registers have the following functions. f0h: scan in/ out control read / write default: 00h b7 b6 b5 b4 b3 b2 b1 b0 sbpda - - - ss sm se sbpdr b0................sbpdr: sound blaster power down request this bit stops the internal state of the sound blaster block. 0: normal (default) 1: stop b1................se: scan enable this bit shifts the internal state by 1 bit. setting a 1 followed by a 0 shifts the internal state. b2................sm: scan mode this bit sets whether to read or write the state. 0: write (default) 1: read b3................ss: scan select this bit gives permission to read or write the internal data to the scan data register. 0: normal operation (do not allow read or write). (default) 1: allow read and write. b7................sbpda: sound blaster power down acknowledgement this bit indicates that the sb block is ready to read or write to the internal state after setting sbpdr. this bit is read only. 0: read/write not possible 1: read/ write possible
YMF754 june 28, 1999 -40- f1h: scan in/ out data read / write default: 00h b7 b6 b5 b4 b3 b2 b1 b0 scan data b[7:0] ..........scan data this is the data port for reading and writing the internal state. f2h: current fm synthesizer index read only default: 00h b7 b6 b5 b4 b3 b2 b1 b0 current fm synthesizer index b[7:0] ..........current fm synthesizer index this register indicates current index of the fm synthesizer. f3h: current fm synthesizer array read only default: 00h b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - cfa b0................cfa: current fm synthesizer arary this bit indicates that the fm synthesizer array is being currently set to array 0 or 1. 0: array 0 (default) 1: array 1 f4h: fm synthesizer / mpu401 status read only default: 80h b7 b6 b5 b4 b3 b2 b1 b0 ffemp ffful - - - - - mpus b0................mpus: mpu401 status this bit indicates current mpu401 status. 0: default mode (intelligent mode) (default) 1: uart mode b6................ffful: fm synthesizer fifo full this bit indicates whether or not fifo followed by the fm synthesizer is full. 0: not full (default) 1: full
YMF754 june 28, 1999 -41- b7................ffemp: fm synthesizer empty this bit indicates whether or not fifo followed by the fm synthesizer is empty. 0: not empty 1: empty (default) i) scan out sbpda=0 sbpdr=1 sbpda=1 sm=1 ss=1 se=1 -> 0 se=1 -> 0 : not ready for scanning internal state data : inhibit further dma, internal state shutdown : ready for scanning internal state data : internal state read out : reading internal state : shifting internal state scan data out 1-bit at a time 8 times n times : internal state scan data out scan data (read) suspend preparation ii) scan in sbpda=0 sbpdr=1 sbpda=1 sm=0 ss=1 : not ready for scanning internal state data : inhibit further dma, internal state shutdown : ready for scanning internal state data : internal state write in : writing internal state : shifting internal state scan data in 1-bit at a time 8 times n times : internal state scan data in scan data (write) resume completion sm=0 ss=0 sbpdr=0 n = 34 byte (total scan data = 268 bit (33 byte x 8 + 4 bit))
YMF754 june 28, 1999 -42- 2-2-4. sb irq status f8h: interrupt flag register read only default: 00h b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - sbi b0................sbi: sb interrupt flag this bit indicates that the sb dsp occurs the interrupt. this bit is read only. thus, read the sb dsp read port to clearing the interrupt and this bit. then, the value of the read port is invalid. 2-3. mpu401 mpu401 block is for transmitting and receiving midi data. it is compatible with uart mode of mpu401. full duplex operation is possible using the 16-byte fifo for each direction, transmitting and receiving. the following shows the mpubase i/o map for mpu401. mpubase (r/w) midi data port mpubase + 1h (r) status register port mpubase + 1h (w) command register port portd7d6d5d4d3d2d1d0 +0h data +1h (w) command +1h (r)/dsr/drr------
YMF754 june 28, 1999 -43- 2-4. joystick joystick block is the port for connecting ibm compatible analog joystick. the following shows the jsbase i/o map for joystick. jsbase (r/w) port d7 d6 d5 d4 d3 d2 d1 d0 +0h jbb2 jbb1 jab2 jab1 jbcy jbcx jacy jacx jacx... joystick a, coordinate x jacy... joystick a, coordinate y jbcx... joystick b, coordinate x jbcy... joystick b, coordinate y jab1... joystick a, button 1 jab2... joystick a, button 2 jbb1... joystick b, button 1 jbb2... joystick b, button 2
YMF754 june 28, 1999 -44- 3. dma emulation protocol the former synthesizer lsi for the isa bus such as the sound blaster used the dma controller (8237: isa dmac) on the system to transfer the sound data from/to the host. for ds-1e, however, isa dmac must be used to transfer the sound data to the sound blaster pro block of the legacy audio block. because signals to connect to the isa dmac are generally not available on the pci bus, there are two ways proposed from the industry to emulate the isa dmac on the pci bus. one is pc/pci and the other is d- dma. ds-1e supports both protocols for transferring sb pro sound data on the pci bus. 3-1. pc/pci ds-1e provides two signals, pcreq# and pcgnt# to realize the pc/pci. the format of the signals is shown below. ds-1e asserts pcreq# and sets pcreq# to high using the pciclk corresponding to the dma channel it is going to use. in addition, ds-1e determines whether the next pci i/o cycle is its own from the channel information that is encoded in pcgnt#. start ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 start bit0 bit1 bit2 0ns 100ns 200ns 300ns 400ns pciclk req# gnt# pcgnt# is encoded as follows. gnt# encodin g bit2 bit1 bit0 gnt# bits 000 dma channel 0 001 dma channel 1 010 dma channel 2 011 dma channel 3 100 reserved 101 dma channel 5 110 dma channel 6 111 dma channel 7 ds-1e supports only 8-bit dma channels (dma channel 0-3). it also only supports single dma transfer.
YMF754 june 28, 1999 -45- 3-2. d-dma ds-1e provides the following registers to support d-dma. d-dma slave configuration register (4c- 4dh) of the pci configuration register is used to set the base address of the slave address. slave address r/w register name base + 0h w base address 0-7 base + 0h r current address 0-7 base + 1h w base address 8-15 base + 1h r current address 8-15 base + 2h w base address 16-23 base + 2h r current address 16-23 base + 3h w base address 24-31 base + 3h r current address 24-31 base + 4h w base word count 0-7 base + 4h r current word count 0-7 base + 5h w base word count 8-15 base + 5h r current word count 8-15 base + 6h w base word count 16-23 base + 6h r current word count 16-23 base + 7h n/a reserved base + 8h w command base + 8h r status base + 9h w request base + ah n/a reserved base + bh w mode base + ch w reserved base + dh w master clear base + eh n/a reserved base + fh r/w multi-channel mask these registers can be accessed by 8-bit or 16-bit bus width. ds-1e supports 8-bit dma transfer only.
YMF754 june 28, 1999 -46- 4. interrupt routing ds-1e supports three types of interrupts, interrupt signal on the pci bus (inta#), interrupt signal on the isa bus (irq[5,7,9,10,11]), and serialized irq. the irqs on ds-1e are routed as shown below. sound blaster pro mpu401 irq selector selector irq sbirq[2:0] isa irq serirq mpuirq[2:0] sien, imod sien=0, imod=1 sien=0, imod=0 sien=1, imod=0 sien=0, imod=1 sien=0, imod=0 sien=1, imod=0 select signal select signal irq5 irq7 irq9 irq10 irq11 serirq# inta# inta pci audio pci audio can only use inta#, but the sound blaster pro and mpu401 blocks of the legacy audio block can use any of the three protocols. the protocol can be switched using 40-43h (legacy audio control register) of the pci configuration register. 4-1. serialized irq serialized irq is a method to encode irqs of 15 channels into one signal. ds-1e provides the serirq# pin to support serialized irq. only one channel out of the 5 channels, irq5, irq7, irq9, irq10, and irq11, can be encoded into the irq/data frame of serialized irq. the irq channel is selected using 40h-43h (legacy audio control register) of the pci configuration register.
YMF754 june 28, 1999 -47- 5. hardware volume control the hardware volume control determines the ac97 master volume without using any software control using the external circuit listed below. two pins, volup# for increasing the volume and voldw# for decreasing the volume, are used. 1k voldw# volup# 1k 1000p 1000p push sw push sw ds-1e provides a shadow register for the ac97 master volume. when the software accesses the ac97 master volume, it is always reflected in the shadow register. bringing the volup# pin low level increments the left and right-channel shadow register by +1.5db respectively. if either one of channel shadow registers have been already set to maximum value (00000b), the corresponding channel shadow register remains in the same value, and the other channel shadow register will only be incremented. if both of channel shadow registers have been already set to maximum values, they remain in the same values. bringing the voldw# pin low level decrements the left and right-channel shadow register by -1.5db respectively. if either one of channel shadow registers have been already set to minimum value (11111b), the corresponding channel shadow register remains in the same value, and the other channel shadow register will only be decremented. if both of channel shadow registers have been already set to minimum values, they remain in the same values. the master volume for the ac97 is updated automatically via the ac-link by setting corresponding values to the shadow registers. when both of the volup# and voldw# pins are at low level at the same time, the mute bit of the shadow register is enabled to automatically set the mute bit of the ac97 master volume via the ac-link. when either one of the volup# or voldw# pins is at low level, mute condition of the ac97 is deactivated via the ac-link. at this point of time, the master volume is set to the value before the mute. when the ac-link is busy (in case the register is controlled by the ac97 control register), shadow register values will be set to the ac97 on the next frame. at this time, busy is set at the ac97 control register. when the master volume is changed or muted depending on the logic level transition status of the volup# and voldw# pins, an interrupt is generated at the host. the interrupt is used to notify the driver that the master volume has been changed. when the ac97 is not connected or it is placed in power down mode, the shadow register values will remain in the same even if the voldw# and volup# pins are at low level.
YMF754 june 28, 1999 -48- 6. digital audio interface ds-1e supports each system of the spdif input/output port compliant with the iec958 specification. 6-1. spdif in spdif input sampling frequency is 32.0khz, 44.1khz or 48.0khz. in ds-1e, sampling rate of the spdif signal incoming from the spdifin pin is converted to 48.0khz in the frequency rate conversion stage in order to process all the signals at 48.0khz frequency. if input sampling frequency is 48.0khz, however, this is resampled at 96.0khz, then decimated into 48.0khz frequency. ds-1e supports a direct recording function which records by input sampling rate of the spdifin pin without converting to 48khz. the input signal applied to the spdifin pin can be also provided as outputs to the spdifout pin. the spdif input is used to be selected between zoomed video port on ymf744b (ds-1s). however, on ds-1e, the both functions can be used at the same time. 6-2. spdif out spdif output is selected from three types of data indicated below: a : dolby digital (ac-3) encoded data b : output data (to be provided to the dac slot on the ac-link) after digital mixing c : input data applied to the spdifin pin when the above a and b data are supplied as outputs, output sampling frequency is fixed at 48 khz, and when the above c data is supplied as an output, output sampling frequency is dependent on the frequency available from the spdifin input pin. control and category codes of the channel status are provided as sampling rate converter, copyright protection available and commercially available recorded software in accordance with the serial copy management system. such a code arrangement allows output data to be digitally copied only to the next generation ones. when input signal to the spdifin pin is provided as output, no modification is made for the channel status, etc., and output data is code-dependent available from the spdifin pin.
YMF754 june 28, 1999 -49- 7. zoomed video port zoomed video port is defined in the pc card standard (pcmcia) applicable to the notebook pc or other systems. this port is used to directly output video and/or audio signals onto the pcmcia bus for d/a conversion process, and connect them directly to the video and/or audio signal processing chips on the pc system. its major applications include mpeg decoder card and video capture card, etc. because the video and/or audio signals on the zoomed video port have been output in synchronized condition, ds-1e mixes it with the other audio signals, and outputs to ac97 or spdif. audio signals to be transferred on the zoomed video port include bit clock (sclk), l/r clock (lrck) and serial data (data), and they are provided as outputs in the format defined below. this is generally called i 2 s format. 1514131211109876543210 1514131211109876543210 left channel right channel sclk data lrck in the zoomed video port, synchronization with a master clock supplied from the bus is inherently required. however, ds-1e can asynchronously process audio signal input via the zoomed video port, eliminating the need for master clock. sampling rate of the audio signals input via the zoomed video port is resampled to 96.0khz sampling frequency at the stage followed by the src block, then converted to 48.0khz sampling rate in the src block stage. sampling rates to be supported on the zoomed video port include 22.05khz, 32.0khz, 44.1khz and 48.0khz. interface connection arrangement between the ds-1e and the zoomed video port is as illustrated below. zvbclk ds-1e zv port zvlrck zvsdi mclk data lrck sclk open the zoomed video port is used to be selected between spdif input on ymf744b (ds-1s). however, on ds-1e, the both functions can be used at the same time.
YMF754 june 28, 1999 -50- 8. multiple ac97 & multi-channel ds-1e allows connection with up to two ac97s, and plays back up to 4-channel pcm data. therefore, the following applications can be realized. 8-1. ac97 digital docking ac97 digital docking can be realized by mounting the secondary ac97 on the docking station side. typical example of digital docking connection between ds-1e and ac97s is represented in the diagram below. primary ac'97 (ac'97 rev2.1) secondary ac'97 ds-1e pc side docking station side cmclk xtl_in bit_clk sync sdata_out sdata_in reset# xtl_in bit_clk sync sdata_out reset# sdata_in cbclk csync csdo csdi0 rst# gpio2 docken# csdi1 dvdd isolation buffer when digital docking interface is made with the main side (pc side) powered on, but docking station side powered off, it may be not desirable for the secondary ac97 that each output signal from the ac-link is applied to the secondary ac97 that remains in powered off state. in order to avoid such a situation, it is necessary to place an additional isolation buffer on the pc side (or docking station side). 8-2. 4-channel speaker system 4-channel speaker system can be realized by the connection of ds-1e with two 2-channel ac97s as described at 8-1. ac97 digital docking or using the ac97 that includes 4-channel d/a converters. then, 4-channel pcm data can be played back at one time.
YMF754 june 28, 1999 -51- electrical characteristics 1. absolute maximum ratings item symbol min. max. unit power supply voltage (pvdd, vdd) v dd3 -0.3 4.6 v power supply voltage (cvdd, lvdd) v dd2 -0.3 3.6 v input voltage v in -0.3 5.75 v operating ambient temperature t op 070c storage temperature t stg -50 125 c note : pvss=vss=lvss=0[v] 2. recommended operating conditions item symbol min. typ. max. unit power supply voltage (pvdd, vdd) v dd3 3.00 3.30 3.60 v power supply voltage (cvdd, lvdd) v dd2 2.30 2.50 2.70 v operating ambient temperature t op 02570c note : pvss=vss=lvss=0[v]
YMF754 june 28, 1999 -52- 3. dc characteristics item symbol condition min. typ. max. unit high level input voltage 1 v in -0.5 - 5.75 v high level input voltage 1 v ih1 *1 0.5v dd3 --v low level input voltage 1 v il1 *1 - - 0.3v dd3 v high level input voltage 2 v ih2 *2 0.7v dd3 --v low level input voltage 2 v il2 *2 - - 0.3v dd3 v high level input voltage 3 v ih3 *3 0.65v dd3 --v low level input voltage 3 v il3 *3 - - 0.35v dd3 v high level input voltage 4 v ih4 *4 2.0 - - v low level input voltage 4 v il4 *4 - - 0.8 v input leakage current i il 0< v in < v dd5 -10 - 10 a high level output voltage 1 v oh1 *5, i oh1 = -0.5ma 0.9v dd3 --v low level output voltage 1 v ol1 *5, i ol1 = 1.5ma - - 0.1v dd3 v high level output voltage 2 v oh2 *6, i oh2 = -100a 0.8v dd3 --v low level output voltage 2 v ol2 *6, i ol2 = 300a - - 0.2v dd3 v high level output voltage 3 v oh3 *7, i oh3 = -2.0ma 0.9v dd3 --v low level output voltage 3 v ol3 *7, i ol3 = 6.0ma - - 0.1v dd3 v high level output voltage 4 v oh4 *8, i oh4 = -0.5ma 2.4 - - v low level output voltage 4 v ol4 *8, i ol4 = 1.5ma - - 0.4 v high level output voltage 5 v oh5 *9, i oh5 = -1.5ma 2.4 - - v low level output voltage 5 v ol5 *9, i ol5 = 4.5ma - - 0.4 v input pin capacitance c in 5 - 15 pf clock pin capacitance c clk 5 - 15 pf idsel pin capacitance c idsel 5 - 15 pf output leakage current i ol -10 - 10 a normal - 75 100 ma power supply current power save (*10) - tbd tbd ma note : top = 0~70c, pvdd=3.3 0.3[v], vdd=3.3 0.3[v], cvdd=2.5 0.2[v], lvdd=2.5 0.2[v] *1: applicable to all pci iuput/output pins and iunput pins. *2: applicable to xi24 pin. *3: applicable to cbclk, csdi0 and csdi1 pins. *4: applicable to zvbclk, zvlrck, zvsdi, gp[7:4], rxd, volup#, voldw#, gpio[2:0], docken#, romdi, spdifin and test# pins. *5: applicable to all pci input/output pins and output pins. *6: applicable to xo24 pin. *7: applicable to crst#, csync, csdo and cmclk pins. *8: applicable to spdifout, romsk, romdo, romcs, gpio[2:0] and txd pins. *9: applicable to irq5, irq7, irq9, irq10 and irq11 pins. *10: all ds-1e power control bits are set to 1.
YMF754 june 28, 1999 -53- 4. ac characteristics 4-1. master clock (fig.1) item symbol min. typ. max. unit xi24 cycle time t xicyc - 40.69 - ns xi24 high time t xihigh 13 - 24 ns xi24 low time t xilow 13 - 24 ns note : top = 0-70c, pvdd=3.3 0.3 v, vdd=3.3 0.3 v, cvdd=2.5 0.2 v, lvdd=2.5 0.2 v t xi24 xicyc t xihigh 1.0 v 1.65 v 2.3 v t xilow fig.1: xi24 master clock timing 4-2. reset (fig.2) item symbol min. typ. max. unit reset active time after power stable t rst 1--ms power stable to reset rising edge t rstoff 10 - - ms reset slew rate - 50 - - mv/ns note : top = 0-70c, pvdd=3.3 0.3 v, vdd=3.3 0.3 v, cvdd=2.5 0.2 v, lvdd=2.5 0.2 v, c l =50 pf rst# cvdd, lvdd pvdd, vdd 2.3 v 3.0 v 0.8 v t rst t rstoff fig.2: pci reset timing
YMF754 june 28, 1999 -54- 4-3. pci interface (fig.3, 4) item symbol condition min. typ. max. unit pciclk cycle time t pcyc 30 - - ns pciclk high time t phigh 11 - - ns pciclk low time t plow 11 - - ns pciclk slew rate - 1 - 4 v/ns t pval (bused signal) 2 - 11 ns pciclk to signal valid delay t pval ( ptp ) (point to point) 2 - 12 ns float to active delay t pon 2--ns active to float delay t poff --28ns t psu (bused signal) 7 - - ns *11 (point to point) 10 - - ns input setup time to pciclk t psu ( ptp ) *12 (point to point) 12 - - ns input hold time for pciclk t ph 0--ns note : top = 0-70c, pvdd=3.3 0.3 v, vdd=3.3 0.3 v, cvdd=2.5 0.2 v, lvdd=2.5 0.2 v, c l =10 pf *11: this characteristic is applicable to req# and pcreq# signal. *12: this characteristic is applicable to gnt# and pcgnt# signal. t pciclk pcyc t phigh 0.3 v dd3 0.4 v dd3 0.5 v dd3 t plow fig.3: pci clock timing pciclk output input tri-state output 1.5 v 1.5 v 1.5 v t pval t pon t poff t psu t ph fig.4: pci bus signals timing
YMF754 june 28, 1999 -55- 4-4. ac97 master clock (fig.5) item symbol min. typ. max. unit cmclk cycle time t cmcyc - 40.69 - ns cmclk high time t cmhigh 8--ns cmclk low time t cmlow 8-ns cmclk rising time t cmr -4.6-ns cmclk falling time t cmf -2.1-ns note : top = 0-70c, pvdd=3.3 0.3 v, vdd=3.3 0.3 v, cvdd=2.5 0.2 v, lvdd=2.5 0.2 v, c l =50 pf t cmclk cmcyc t cmf t cmr t cmhigh 0.2 v dd3 0.5 v dd3 0.8 v dd3 t cmlow fig.5: master clock timing for ac97
YMF754 june 28, 1999 -56- 4-5. ac-link (fig.6) item symbol condition min. typ. max. unit cbclk cycle time t cbicyc - 81.4 - ns cbclk high time t cbihigh 35 40.7 45 ns cbclk low time t cbilow 35 40.7 45 ns csync cycle time t csycyc - 20.8 - s csync high time t csyhigh -1.3-s csync low time t csylow - 19.5 - s cbclk to signal valid delay t cval *13 - - 20 ns output hold time for cbclk t coh *13 0 - - ns input setup time to cbclk t cisu *14 15 - - ns input hold time for cbclk t cih *14 5 - - ns warm reset width - 1.3 - s note) top = 0-70c, pvdd=3.3 0.3 v, vdd=3.3 0.3 v, cvdd=2.5 0.2 v, lvdd=2.5 0.2 v, c l =50 pf *13: this characteristic is applicable to csync and csdo signal. *14: this characteristic is applicable to csdi signal. cbclk sync csdi csdo 0.8 v 1.5 v 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v 1.5 v 2.0 v t cbihigh t cval t cbilow t cbicyc t cval t coh t csycyc t csyhigh t coh t csylow t cisu t cih fig.6: ac-link timing
YMF754 june 28, 1999 -57- 4-6. zoomed video port (fig.7) item symbol min. typ. max. unit zvlrck delay time t slrd 2--ns zvlrck setup time t slrs 32 - - ns zvbclk low time t sclkl 22 - - ns zvbclk high time t sclkh 22 - - ns zvsdi setup time t sds 32 - - ns zvsdi hold time t sdh 2--ns note : top = 0-70c, pvdd=3.3 0.3 v, vdd=3.3 0.3 v, cvdd=2.5 0.2 v, lvdd=2.5 0.2 v, c l =50 pf t sdh t sds t sclkh t sclkl t slrs t slrd zvlrck zvsclk zvsdi fig.7: zoomed video port timing
YMF754 june 28, 1999 -58- external dimensions YMF754-v 102 65 103 128 138 39 64 p-0.50typ. 0.15typ. or 0.17typ. (lead thickness) 1.70max. 0 min. (stand off) unit : mm 22.000.40 20.000.30 14.000.30 0.200.10 16.000.40 (1.00) 0-15? 0.500.30 1.400.20 the shape of the molded corner may slightly different from the shape in this diagram. the figure in the parenthesis ( ) should be used as a reference. plastic body dimensions do not include burr of resin. unit : mm note : the lsis for surface mount need especial consideration on storage and soldering conditions. for detailed information, please contact your nearest agent of yamaha.
YMF754 june 28, 1999 -59- YMF754-r 96 97 128 132 33 64 65 p-0.40typ. unit : mm 16.000.40 14.000.30 14.000.30 0.160.10 16.000.40 (1.0) 0-10? 0.500.20 1.400.20 1.70max. 0 min. (stand off) lead thickness : 0.125typ. or 0.15typ. the shape of the molded corner may slightly different from the shape in this diagram. the figure in the parenthesis ( ) should be used as a reference. plastic body dimensions do not include burr of resin. unit : mm note : the lsis for surface mount need especial consideration on storage and soldering conditions. for detailed information, please contact your nearest agent of yamaha.
YMF754 june 28, 1999 -60- important notice 1. yamaha reserves the ri g ht to make chan g es to its products and to this document without notice. the information contained in this document has been carefull y checked and is believed to be reliable. however, yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. these yamaha products are desi g ned onl y for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support e q uipment, nuclear facilities, critical care e q uipment or an y other application the failure of which could lead to death, personal in j ur y or environmental or propert y dama g e. use of the products in any such application is at the customer's sole risk and expense. 3. yamaha assumes no liability for incidental, consequential or special damages or injury that may result from misapplication or improper use or operation of the products. 4. yamaha makes no warranty or representation that the products are subject to intellectual property license from yamaha or anythird party, and yamaha makes no warranty or representation of non-infringement with respect to the products. yamaha specifically excludes any liability to the customer or any third party arising from or related to the products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. examples of use described herein are merely to indicate the characteristics and performance of yamaha products. yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title. note) the specifications of this product are subject to improvement change without prior notice. agency yamaha corporation address inquires to : semi-conductor sales department - head office 203, matsunokijima, toyooka-mura. iwata-gun, shizuoka-ken, 438-0192 tel. +81-539-62-4918 fax. +81-539-62-5054 - tokyo office 2-17-11, takanawa, minato-ku, tokyo, 108-8568 tel. +81-3-5488-5431 fax. +81-3-5488-5088 - osaka office 1-13-17, namba naka, naniwa-ku, osaka city, osaka, 556-0011 tel. +81-6-6633-3690 fax. +81-6-6633-3691 - u.s.a. office yamaha system technology. 100 century center court, san jose, ca 95112 tel. +1-408-467-2300 fax. +1-408-437-8791

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